Technology limitations for N/sup +//P/sup +/ polycide gate CMOS due to lateral dopant diffusion in silicide/polysilicon layers

Abstract

The device degradation of dual-polycide-gate N/sup +//P/sup +/ CMOS polycide transistors due to the lateral diffusion of dopants in the silicides is studied using a coupled 2-D process and device simulator. Design rule spacings between the NMOS and the PMOS transistor are given for various NMOS:PMOS gate area ratios and thermal processing conditions. The simulations show that contrary to previous findings, micrometer and submicrometer spacings are possible for certain silicide technologies using low-temperature or short higher-temperature furnace steps. Simulations show that CoSi/sub 2/ and TiSi/sub 2/ appear to be better candidates for submicrometer dual-gate applications than WSi/sub 2/.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>