A model for electric degradation of interconnect low-k dielectrics in microelectronic integrated circuits

Abstract

The low-k dielectric used in interconnect systems of advanced microelectronic devices tends to degrade faster than gate oxide under electric field. The scaling down of the spacing between metal lines to a few tens of nanometers in emerging complementary metal oxide semiconductor technologies calls for re-examining and refining of existing degradation models for ensuring the reliability of future technology nodes without compromising performance. This paper suggests a simple model to explain the nature of the field- and current-induced degradation by taking the electron temperature into account. It is based on experimentally observed trapped charge and current versus time behavior under constant voltage stress. The model explains the low observed activation energy but predicts its increase at operating conditions. It suggests that the commonly used E model may be too conservative for the extrapolation of dielectric lifetime measured under accelerated test (high voltage) conditions to operating voltages. It also predicts that the use of the recently proposed E model is safe for reliability engineering purposes, although it does not describe the full degradation process complexity adequately.