Planariation technology for Josephson integrated circuits

Abstract

Planarization technology has enabled completion of the multi-level layer structure, which is essential to the achievement of large-scale integration and high-speed operation. A new etch-back planarization technology, using 2000-molecular weight polystyrene, has been developed for Josephson integrated circuits (IC's). This technology has been applied to fabricating the multilevel layer structure in magnetic coupled gates. The results, indicated by their cross-sectional SEM photographs and measured breakdown voltages, show that excellent planarity was achieved in this structure.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>