Fast, minimal decoding complexity, systematic (13,8) single-error-correctingcodes for on-chip DRAMapplications

Abstract

Fast, minimal decoding complexity (13, 8) binary systematic single-error-correcting codes are proposed for on-chip DRAM applications. These (13, 8) codes allow fast single error correcting with one extra parity bit penalty and can be used in combinational circuits with minimal (ultimate) decoding complexity.