Parity Checking
Parity Checking is a fault-detection method in combinational logic and memory systems that appends a redundant bit to a data word to ensure the total number of 1s is either even or odd, thereby enabling the detection of single-bit errors during transmission or storage.
181
Publications
7K
Citations
409
Authors
186
Institutions
Publications per year
2017–2026
13
181
1–5 of 181
409
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Techniques of Informatics and Microelectronics for Integrated Systems Architecture, France
4 publications · 230 citations
4
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4
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3
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3
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1–5 of 409
186
Stanford University
Stanford, United States
7 h-index
16 publications
556 citations
University of Potsdam
Potsdam, Germany
7 h-index
19 publications
631 citations
IBM (United States)
Armonk, United States
6 h-index
8 publications
250 citations
Techniques of Informatics and Microelectronics for Integrated Systems Architecture
Grenoble, France
5 h-index
10 publications
545 citations
University of Illinois Urbana-Champaign
Urbana, United States
5 h-index
11 publications
465 citations
University of Michigan
Ann Arbor, United States
4 h-index
9 publications
351 citations

Centre National de la Recherche Scientifique
Paris, France
4 h-index
10 publications
318 citations
Universitat Politècnica de Catalunya
Barcelona, Spain
3 h-index
6 publications
234 citations
1–8 of 186
15 publications · 390 citations
13
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4 publications · 160 citations
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3 publications · 176 citations
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3 publications · 142 citations
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3 publications · 65 citations
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