Parity Checking

Parity Checking is a fault-detection method in combinational logic and memory systems that appends a redundant bit to a data word to ensure the total number of 1s is either even or odd, thereby enabling the detection of single-bit errors during transmission or storage.

181

Publications

7K

Citations

409

Authors

186

Institutions

Publications per year

2017–2026

13

Authors

409

  1. EM
    E.J. McCluskey

    Stanford University, United States

    7 publications · 222 citations

    7

    h-index

  2. MN
    M. Nicolaidis

    Techniques of Informatics and Microelectronics for Integrated Systems Architecture, France

    4 publications · 230 citations

    4

    h-index

  3. MG
    Michael Gössel

    University of Potsdam, Germany

    4 publications · 93 citations

    4

    h-index

  4. VO
    V. Ocheretnij

    University of Potsdam, Germany

    3 publications · 52 citations

    3

    h-index

  5. RK
    Ramesh Karri

    New York University, United States

    3 publications · 177 citations

    3

    h-index

1–5 of 409

Venues

  1. IEEE Transactions on Computers

    15 publications · 390 citations

    13

    h-index

  2. Electronics Letters

    4 publications · 160 citations

    4

    h-index

  3. Optics Communications

    3 publications · 176 citations

    3

    h-index

  4. IEEE Design & Test of Computers

    3 publications · 142 citations

    3

    h-index

  5. 3

    h-index

1–5