2.5 A 0.25pJ/b 0.7V 16Gb/s 3-tap decision-feedback equalizer in 65nm CMOS

Abstract

In this work, a DFE is presented that is designed specifically to operate at low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> and scale well in energy-efficiency. To achieve this goal, the following innovations are introduced: 1) fast and energy-efficient charge-based latch and sample-and-hold (S/H) topologies; 2) a CMOS-clocked quarter-rate DFE architecture with summer gain and power optimization; 3) an integrating summer with a compact common-mode restoration circuit. Leveraging these techniques, the DFE is capable of operating at or below 0.7V, with an energy efficiency of or better than 0.25pJ/bit.