A 1.5 ns 256 kb BiCMOS SRAM with 11 k 60 ps logic gates

Abstract

The authors present a chip with 1.5-ns access SRAM (static random access memory) and 60-ps logic gates that uses a BiCMOS memory technology with ECL (emitter coupled logic)-CMOS circuits and a 0.5- mu m BiCMOS process providing double-polysilicon bipolar transistors. The chip consists of a gate array and two RAM blocks. The RAM block has four RAM macros, a custom logic macro and a write-pulse generator. A RAM macro contains two 1-kW*32-b arrays with bit redundancy and peripheral circuits. Input/output circuits are at the chip periphery. The RAM operates over a wide range of the supply voltage. Measured output-latch path delay is 2.4 ns at VEE=-4 V. RAM access time is 1.5 ns. Write pulse width is 1.3 ns.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>