E-mode planar L<inf>g</inf> = 35 nm In<inf>0.7</inf>Ga<inf>0.3</inf>As MOSFETs with InP/Al<inf>2</inf>O<inf>3</inf>/HfO<inf>2</inf> (EOT = 0.8 nm) composite insulator

Abstract

We have successfully demonstrated a three-step recess process to fabricate high performance E-mode planar InGaAs MOSFETs. Our devices feature a composite gate insulator with InP/Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> . An L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> =35 nm InGaAs MOSFET with EOT = ~ 0.8 nm exhibits V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> = 0.17 V, R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> = 285 Ohm-μm, DIBL = 135 mV/V and S = 115 mV/dec, as well as a negligible dispersion and hysteresis behavior. Most importantly, our device displays the highest value of g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m_max</sub> > 2 mS/μm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.5 V in any III-V MOSFETs.