Cache memory organization to enhance the yield of high performance VLSI processors

Abstract

The authors study the tolerance of defects faults in cache memories. They argue that, even though the major components of a cache are linear RAMs (random-access memories), traditional techniques used for fault/defect tolerance in RAMs may be neither appropriate nor necessary for cache memories. They suggest a scheme that allows a cache to continue operation in the presence of defective/faulty blocks. Results are presented of an extensive trace-driven simulation analysis that evaluates the performance degradation of a cache due to defective blocks. From the results it is seen that the on-chip caches of VLSI processors can be organized so that the performance degradation due to a few defective blocks is negligible. The authors conclude that by tolerating such defects without a noticeable performance degradation, the yield of VLSI processors can be enhanced considerably.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>