11.7 A 240mW 16b 3.2GS/s DAC in 65nm CMOS with <-80dBc IM3 up to 600MHz

Abstract

Advanced wireless cellular infrastructure systems require DACs with high spectral purity over a wide bandwidth and which are fit for integration of multiple transmit channels with DSP. This calls for IM3 linearity better than -80dBc up to high frequencies and low power dissipation. In this paper, a high-speed current-steering DAC is reported that combines low power and high linearity, enabled by a 3-dimensional sort-and-combine (3D-SC) calibration technique, CML switch-driving circuitry, and switch cascoding. It achieves similar linearity at significantly reduced power compared to a state-of-the-art high-linearity DAC [1] while its IM3 performance is more than 10dB better than the multi-GS/s low-power DAC in [2]. The 16b 3.2GS/s DAC is implemented in a 65nm CMOS process and achieves -80dBc IM3 up to 600MHz while dissipating 240mW from 1.2V and 3.3V supplies.