New calibration technique for current-steering DACs

Abstract

Attaining high matching property of the current sources is very important for the design of high-speed high-accuracy current-steering DACs. This paper presents a novel calibration technique-complete-folding, which achieves the high matching accuracy by selectively regrouping current sources into a fully binary-weighted array based on the current comparisons after chip fabrication. The implementation only requires an analog current comparator and some digital circuitry. The minimum requirement of analog circuits makes the complete-folding calibration suitable for the DAC design in the low-voltage process. Statistical results with a behavioral model of a 14-bit segmented DAC in MATLAB show that complete-folding calibration can reduce the total gate area of current sources by a factor of almost 1200 compared to that using intrinsic-accuracy method. Additional results also show that the new calibration technique has the superior performance in compensating random mismatch errors compared with state-of-the-art.