All-Copper Chip-to-Substrate Interconnects Part II. Modeling and Design

Abstract

A fabrication technique involving electro- and electroless copper deposition was used to produce all-copper chip-to-substrate interconnects. This process electrolessly joins copper pillars, followed by annealing at . The process is tolerant to in-plane and through-plane misalignment and height variations. The mechanical compliance and electrical performance of copper-pillar chip-to-substrate interconnects is modeled in this paper. The elastic, thermomechanical behavior and electrical performance of the chip-to-substrate interconnects are related to the geometric parameters of the pillars (pitch, diameter, and aspect ratio) and physical properties of the interconnects (yield stress, coefficient of thermal expansion, Young's modulus, Poisson's ratio, and electrical conductivity). The optimum pillar design is a trade-off between the mechanical compliance of the copper pillars and parasitic electrical effects. Copper pillars with a diameter of and height of are mechanically compliant and have parasitic inductance and capacitance less than and , respectively. A polymer collar improves the design space to diameter and height from 441 to .