Low k 1 logic design using gridded design rules

Abstract

Dimensions for 32nm generation logic are expected to be ~45nm. Even with high NA scanners, the k₁ factor is below 0.32. Gridded-design-rules (GDR) are a form of restricted design rules (RDR) and have a number of benefits from design through fabrication. The combination of rules and topologies can be verified during logic technology development, much as is done with memories. Topologies which have been preverified can be used to implement random logic functions with "hotspot" prevention that is virtually context-independent. Mask data preparation is simplified with less aggressive OPC, resulting in shorter fracturing, writing, and inspection times. In the wafer fab, photolithography, etch, and CMP are more controllable because of the grating-like patterns. Tela Canvas^TM GDR layout was found to give smaller area cells than a conventional 2D layout style. Variability and context independence were also improved.