IEEE Micro · 2001 · 50 citations · 9 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureLow-power DesignMemoryCachingMemory HierarchyMemory Hierarchy DesignMemory Hierarchy OptimizationMemory Subsystem DesignCache DesignCache LatencyCache Memory DesignCache OptimizationMemory Access LatencyMemory LatencyMemory Latency OptimizationMemory Latency Reduction
Cached DRAM adds a small cache onto a DRAM chip to reduce average DRAM access latency. The authors compare cached DRAM with other advanced DRAM techniques for reducing memory access latency in instruction-level-parallelism processors.
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Memory bandwidth limitations of future microprocessors
Doug Burger, James Goodman, Alain Kägi · 1996 · 394 citations · Full text
A performance comparison of contemporary DRAM architectures
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