2006 · 23 citations · 0 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMemoryMicroelectronicsEmbedded Memory BlocksEnergy-efficient Embedded SystemsLeakage Power ReductionMemory DevicesMemory Subsystem DesignPower ManagementData RetentionEnergy-efficient Memory DesignEnergy-efficient Memory SystemsLow-power Memory ArchitectureLow-power Memory CircuitsMemory Power OptimizationNon-volatile Memory DesignPower-efficient Memory Design
An extended data retention (EDR) sleep mode with ECC and MT-CMOS is proposed for embedded DRAM power reduction. In sleep mode, the retention time improves by 8 times and the leakage current is reduced to 13% of the normal operation mode. Since ECC scrubbing operates only in the EDR sleep mode, read/write performance is not degraded. A 65nm low-power embedded DRAM macro featuring 400MHz operation and 0.39mW of data-retention power is realized