IEEE Journal of Solid-State Circuits · 2000 · 50 citations · 14 references
EngineeringElectrical EngineeringAnalog ElectronicsMicroelectronicsSemiconductor DevicesCmos Circuit DesignHigh-frequency Semiconductor DevicesMicrowave Integrated CircuitsNoise In Analog CircuitsNoise In Electronic DevicesRadio-frequency Integrated CircuitsBuried Channel DevicesCmos Analog Circuit DesignCmos Analog Integrated CircuitsCmos OscillatorsCmos Radio-frequency CircuitsIntegrated Circuit NoisePhase NoisePower Consumption
A packaged 1.1-GHz CMOS voltage-controlled oscillator (VCO) with measured phase noise of -92, -112, and -126 dBc/Hz at 10-, 100-, and 600-kHz offsets is demonstrated. According to J. Craninekx et al. (1997), these satisfy the GSM requirements. The extrapolated phase noise at a 3 MHz offset is -140 dBc/Hz. The power consumption is 6.8 and 12.7 mW at V/sub DD/=1.5 and 2.7 V, respectively. The VCO is implemented in a low-cost 0.8-/spl mu/m foundry CMOS process, which uses p+ substrates with a p-epitaxial layer. Buried channel PMOS transistors are exclusively used for lower 1/f noise. The inductors for the LC tanks are implemented using a series combination of an on-chip spiral inductor, four bond wires, and two package leads to increase Q. This technique requires no extra board space beyond that needed for the additional package leads.
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