Formal modeling and synthesis of programmable logic controllers

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	Year	Citations
A theory of timed automata Rajeev Alur, David L. Dill Theoretical Computer Science EngineeringFormal MethodsAutomaton NetworkAutomaton OperationComputer Science	1994	6.4K
Timed Automata Rajeev Alur Computer Aided Verification Clock ValuationsEngineeringRuntime VerificationProgram AnalysisSystem Specification	1999	453
Modelling and verification of program logic controllers using timed automata Ruikang K. Wang, Xiaoyu Song, Musong Gu IET Software EngineeringVerificationModel CheckingEmbedded SystemsSoftware Analysis	2007	16
Verification and Implementation of Dependable Controllers Krzysztof Sacha State Machine DiagramEngineeringVerificationIndustrial Control SystemModel Checking	2008	16

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