Abnormal Disturbance Mechanism of Sub-100 nm NAND Flash Memory

Abstract

An abnormal program disturbance mode was found in 32-string NAND flash memory which was fabricated with 0.09 µm complimentary metal–oxide–semiconductor shallow trench isolation (CMOS STI) process technology. This new disturbance mainly occurs in cells next to source select line (SSL) transistor and is not suppressed even when program bias is not applied. This is strongly related to the boosted channel bias level and the interface state which is located between the tunnel oxide and the silicon substrate. This unexpected program disturbance is a hot carrier program which results from the high electric field between the SSL transistor and its nearest cell and the leakage current to the boosted channel. The leakage current to the channel is due to the interface state of the SSL transistor, not the gate induced drain leakage (GIDL) effect. We present a brief model of this abnormal program disturbance mechanism.