A completely integrated single-chip PLL with a 34 GHz VCO using 0.2 /spl mu/m E-/D-HEMT-technology

Abstract

A completely integrated single-chip phase locked loop based on a 0.2 /spl mu/m gate length enhancement/depletion AlGaAs-GaAs-AlGaAs-HEMT technology has been designed and characterized. The chip contains a VCO with 34 GHz center frequency, a dynamic frequency divider by two, a static divider by eight, a phase detector, and a loop filter. The chip size is 2.0/spl times/1.5 mm/sup 2/. The power consumption is 1.2 W at a supply voltage of -5.0 V. The locking range is approximately /spl plusmn/700 MHz. The phase noise of locked PLL is -83 dBc/Hz at 100 kHz and -102 dBc/Hz at 1 MHz offset from the carrier frequency, respectively.