Implementation of a high speed multiplier using carry lookahead adders

Abstract

This paper examines a modification to the Wallace/Dadda Multiplier to use carry lookahead adders instead of full adders to implement the reduction of the bit product matrix into the two numbers that are summed to make the product. Four bit carry lookahead adders are used in the reduction in place of individual full adders. Each carry lookahead adder reduces up to 9 partial products (instead of 3 with a full adder) while taking the same amount of time. This leads to fewer reduction stages than a traditional Wallace/Dadda Multiplier. The results show that 1 fewer stage is required for 4 by 4, 8 by 8, and 16 by 16 bit multipliers and 2 stages are saved for larger multipliers.