Worst-Case Analysis of a Resistor Memory Matrix

Abstract

The worst-case output voltage ratio V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</inf> (1) <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">min</inf> /V <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</inf> (0) <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</inf> is derived for a resistor memory matrix having a finite resistance ratio for the bit elements. It is found that the resistance ratio need not be large, and ratios greater than ten are usually sufficient. Input power and output voltage tradeoffs are also discussed.