IEE Proceedings - Computers and Digital Techniques · 1996 · 15 citations · 2 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysParallel ComputingDigital Signal ProcessingField-programmable Gate Array ArchitectureParallel ArchitecturesParallel Computer ArchitecturePipeline ParallelismDigital Signal Processing BlocksFilter Bank DesignProcessor ConfigurationSystolic Array DesignSystolic ArraysThroughput
Recurrence relations and fully pipelined novel cell-level systolic architectures are suggested for massively parallel implementation of two-dimensional FIR and linear phase FIR filters. Owing to the higher level of parallelism, the proposed structures would yield more throughput over the existing structures. Besides, it can be flexibly configured according to the throughput requirement of the application for the chosen processor technology for cost-effective implementation.
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