Conductivity behavior in polycrystalline semiconductor thin film transistors

TLDR

A grain‑boundary trapping model is used to interpret the ion‑implantation effects, allowing extraction of trap density, donor density, grain size, and mobility, and is validated on CdSe, poly‑Si, and laser‑annealed poly‑Si TFTs. Ion implantation of CdSe TFTs with Cr, Al, or B produces a steep conductivity rise above a threshold dose and modulated transistor behavior without annealing, and the model accurately predicts leakage and drain currents, with thermal annealing further influencing performance.

Abstract

CdSe thin film transistor (TFT) structures which have been ion implanted with 50 keV 52Cr, 50 keV 27Al, or 15 keV 11B have a very steeply rising conductivity above some threshold dose and exhibit modulated transistor characteristics over certain ranges of implant dose, even though there is no thermal annealing during or after ion implantation. These results are interpreted using a model based on grain boundary trapping theory. The dependence of leakage current on implant dose, and of drain current (at a fixed dose) on gate voltage are described very well by this model, when the drain voltage is very small. Using this simple model, the important parameters of the polycrystalline CdSe film, namely the trap density per unit area in the grain boundary, the donor density, grain size, and electron mobility can be deduced. The effect of thermal annealing on implanted and unimplanted CdSe TFT’s has also been studied and the model appears to give a general description of the conductivity behavior in polycrystalline semiconductor TFT’s. This is illustrated by applying the model to devices fabricated by other groups from polycrystalline CdSe, poly-Si and laser-annealed poly-Si semiconductor layers.