Top-contact organic transistors and complementary circuits fabricated using high-resolution silicon stencil masks

Abstract

Here we report on top-contact organic TFTs and complementary circuits fabricated using stencil masks with a resolution of 1 μm. The stencil masks were manufactured on silicon-on-insulator (SOI) wafers, with the buried SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> serving as an etch stop during the formation and patterning of the Si membrane, which has a thickness of 20 μm [10,11]. Openings in the Si membrane were created by electron-beam lithography and dry etching from the wafer front side. Over an area of 20x20 mm2 the bulk silicon was then removed by etching from the wafer back side (using a SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> masking layer), leaving the patterned membrane anchored to a robust 5-mm wide wafer frame.