Spacer double patterning technique for sub-40nm DRAM manufacturing process development

Abstract

Pursuit of lower k₁ for pushing the resolution limit becomes one of the most demanding tasks to meet stringent patterning requirements in next generation lithography. Particularly, the patterning of densely packed array devices with periodic and symmetric features is among the most challenging missions to enable high density memory chips to quickly move forward as projected by Moore's Law. As dictated by the physical limitation of optical system design, current immersion scanners are not capable of reliably printing feature sizes down to sub-40nm regime unless resorting to high index fluids or other effective Resolution Enhancement Techniques (RETs). Fortunately, recent prosperous progress in double patterning technique seems to give realistic hope as a straightforward bridge between the current immersion scanners [1] and the relatively immature EUV scanners [2]. State-of-the-art double patterning technique [3] includes the well known LLE (Litho-Litho-Etch) [4], LELE (Litho-Etch-Litho-Etch) [5], self-aligned [6] and other approaches [7]. Among them the self-aligned approach is regarded as more appropriated for mass production of high density arrays due to less concerned of overlay budget [8]. In this paper, we studied the integrated lithography performance of one innovative self-aligned double patterning scheme for the demonstration of sub-40nm capability by the use of the most advanced 193nm dry scanner. In addition, silicon containing bottom reflective coating (BARC) was employed for the CD trimming in order to optimize the lithography & etch process windows [9]. A 37.5nm half-pitch L/S memory array with well controlled line edge roughness (LER) was successfully demonstrated in this work by the above mentioned selfaligned spacer approach. The equivalent k₁~0.146 was readily achieved without too much complex integration, which is especially suitable for the future high density memory arrays as in FLASH or DRAM.