Interfacing Cores and Routers in Network-on-Chip Using GALS

Abstract

Network-on-Chip (NoC) architectures consist of heterogeneous cores connected through an interconnection network. The communication between the nodes is achieved by routing packets rather than wires. It supports high degree of reusability, scalability, and parallelism in communication. NoC has emerged as a new paradigm for designing core based System-on-Chip (SoC). The success of NoC design relies greatly on the standardization of the interfaces between IP cores and network fabric. The cores may have different frequency, whereas the network router also may operate at different frequency as per design. So, there is a possibility of loosing some data due to improper synchronization. In this paper, we propose the design of Network Interface to make the IP core compatible to network switch, enabling communication between them. We also present how Globally Asynchronous Locally Synchronous (GALS) style of communication has been implemented in our NOC by using FIFO in mixed clock system.