EngineeringComputer EngineeringElectrical EngineeringAnalog ElectronicsLow-power DesignSystem-on-chip DesignClock ManagementCmos Circuit DesignDynamic Power ReductionLow-power Digital Circuit DesignPower ManagementPower OptimizationClock Data RecoveryClock RecoveryEqualizationEthernetGigabit EthernetHigh-speed Cmos DesignPower ConsumptionPower Consumption Optimization
The power consumption of broadband receivers becomes particularly critical in multi-lane applications such as the 100 Gigabit Ethernet. However, the powerspeed trade-off tends to intensify at higher rates, making it a greater challenge to reach the generally-accepted efficiency of 1mW/Gb/s. Prominent among the power-hungry receiver building blocks are the clock-and-data-recovery circuit, the deserializer, and the front-end equalizer. The use of charge-steering techniques has shown promise for the low-power implementation of the first two functions [1]. This paper introduces a half-rate 25Gb/s equalizer employing charge steering and achieving an efficiency of 0.232mW/Gb/s.
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