A Simple and Useful Layout Scheme to Achieve Uniform Current Distribution for Multi-Finger Silicided Grounded-Gate NMOS

Abstract

The influence of the contact-to-contact space on the ESD performance of multi-finger silicided ground-gate NMOS (GGNMOS) is investigated. We find that the conventional contact layout, which has short contact-to-contact space, induces current localization, and degrade the device ESD performance. Here we discuss how to design a ballast resistor for silicided multi-finger GGNMOS and show that lengthening the contact spacing can significantly improve device ESD performance (It2, HBM and MM). This improvement eliminates the short channel induced degradation of thin oxide device ESD