CHARGE COUPLED 8-BIT SHIFT REGISTER

Abstract

An 8-bit shift register has been developed based on the charge-coupled device concept. The device configuration is essentially that of a linear array of 26 closely spaced MOS capacitors with a p-n junction at either end. A packet of charge is inserted into the first capacitor from one of the p-n junctions and then transferred down the array in a potential well created by sequential pulsing of the electrode potentials. A high-charge transfer efficiency of greater than 99.9% per electrode has been obtained in this device for transfer times of 2μ sec. The use of the device as an 8-bit shift register and a line imaging device are demonstrated thereby further verifying the charge-coupled device concept and showing the basic feasibility of developing charge-coupled devices for shift registers, logic operations, and optical imaging applications.