Charge accumulation effects on profile distortion in ECR plasma etching

Abstract

Recent studies of electron cyclotron resonance (ECR) plasma etching for fabricating the gate electrode of MOS LSIs indicate a serious problem in the etched profiles. The problem is a local pattern distortion which is commonly called notch. The notch has a characteristic dependence on the pattern layout and plasma conditions. For determining the validity of the model which suggests that the cause of notch is charge accumulation of fine patterns, plasma parameters are measured by electrostatic probes and relationships between the notch and the plasma properties are investigated. Lowering the electron temperature parallel to the wafer surface is one of the most effective techniques for eliminating the notch. A lower electron temperature is achieved by moving the wafer farther from the ECR region. Increasing rf bias is effective for reducing the notch. However, elimination of notch with rf bias is due to an increased ion energy. Thus high selectivity, which requires low ion energy, cannot be achieved while simultaneously preventing the notch. Modifying the distribution of plasma potential which decreases toward the wafer reduces the notch in spite of the higher ion current density.