Chip-package interaction: Challenges and solutions to mechanical stability of Back end of Line at 28nm node and beyond for advanced flip chip application

Abstract

Fhis paper discusses the extensive development work carried out by GLOBALFOUNDRIES to mitigate chip-package interaction (CPI) risks for the silicon Backend of Line (BEOL) during IC package assembly. Particularly, material property data for different ultra low k (ULK) materials, CPI qualification results and key findings made during the technology development are discussed. Newly developed test and modeling methods to expedite technology learning are also described in detail.