An efficient equivalence checker for combinational circuits

Abstract

Article An efficient equivalence checker for combinational circuits Share on Author: Yusuke Matsunaga FUJITSU LABORATORIES LTD, Kawasaki 211-88, Japan FUJITSU LABORATORIES LTD, Kawasaki 211-88, JapanView Profile Authors Info & Claims DAC '96: Proceedings of the 33rd annual Design Automation ConferenceJune 1996 Pages 629–634https://doi.org/10.1145/240518.240637Online:01 June 1996Publication History 70citation315DownloadsMetricsTotal Citations70Total Downloads315Last 12 Months3Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access