Ionized physical vapor deposition of integrated circuit interconnects

Abstract

Interconnects, once the technological backwater of integrated circuit technology, now dominate integrated circuit cost and performance. As much as 90 percent of the signal delay time in future integrated circuit designs will be due to the interconnection of semiconductor devices while the remaining 10 percent is due to transistor-related delay. This shifts the thrust of critical research toward an improved understanding of interconnect science and technology. Shrinking circuit geometries will require high aspect ratio (AR) vias to interconnect adjacent metal layers. By the year 2007 it is predicted that logic circuits will use 6 to 7 interconnected metal layers with via ARs of 5.2:1. Memory will need fewer layers, but ARs as high as 9:1. In this paper, the demands of interconnect technology will be reviewed and the opportunities for plasma-based deposition of vias will be discussed. One promising new method of fabricating high-aspect ratio vias is ionized physical vapor deposition (I-PVD). The technique economically creates a unidirectional flux of metal which is uniform over 200–300 mm diameter wafers. Since metal ejected by conventional sputtering is primarily neutral and exhibits a cosine angular velocity distribution, sputtered metal atoms do not reach the bottom of high AR vias. By sputtering these atoms into a moderate pressure (4 Pa), high-density Ar plasma, however, the metal atoms are first thermalized and then ionized. The ions are then readily collimated by the plasma sheath and directionally deposited into narrow, deep via structures. Experiments have consistently shown that over 80% of the metal species are ionized using I-PVD. The physical mechanisms responsible for ionization will be discussed from both an experimental and modeling perspective and the spatial variation of metal ionization is experimentally determined.