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Improvement in Antimony-Doped Ultrashallow Junction Sheet Resistance by Dopant Pileup Reduction at the SiO<sub>2</sub>/Si Interface
12
Citations
4
References
2000
Year
Materials ScienceMaterials EngineeringElectrical EngineeringSemiconductor TechnologyEngineeringLow-energy Sb ImplantationDopant Pileup ReductionNanoelectronicsBias Temperature InstabilityApplied PhysicsDopant LossSb PileupSemiconductor MaterialSemiconductor Device FabricationMicroelectronicsSemiconductor Device
Ultrashallow low-resistive junction formation has been investigated for sub-100-nm metal oxide semiconductor field effect transistors (MOSFETs) using low-energy Sb implantation and the rapid thermal annealing (RTA) technique. The Sb pileup at the Si/SiO 2 interface and the resulting dopant loss observed in the furnace annealing cases was reduced by the RTA technique. As a result, the sheet resistance of 19-nm-deep junctions was decreased to 0.84 kΩ/sq. By increasing the implantation dose to 1×10 14 cm -2 , a junction depth of 24 nm and sheet resistance of 0.45 kΩ/sq. were obtained. In the case of As, the pileup was not suppressed even with RTA. These results indicate that Sb is superior to As as a dopant for ultrashallow extension formations.
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