Design of passive UHF RFID tag in 130nm CMOS technology

Abstract

This paper presents a low-power, passive, UHF RFID tag design compatible with EPC <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TM</sup> C1G2 protocol. In order to reduce its cost, diode-connected NMOS in a standard CMOS technology is used instead of Schottky diodes. With the help of low-threshold-voltage, triple-well NMOS, a minimum input power of -7.6 dBm is achieved. A sub-1 V, low temperature-coefficient voltage reference using self-biased mutual compensation is proposed without large resistors to save the chip area. In addition, an energy-aware irregular clock structure, together with clock gating, achieves low power consumption in the baseband processor. The whole tag is implemented in a 130 nm CMOS technology and the total chip area is 1200 mum times 1220 mum.