A 40 nm LP CMOS PLL for high-speed mm-wave communication

Abstract

A phase-locked loop (PLL) that can be used in a zero-IF radio architecture with beamforming for AV-OFDM with 16-QAM modulation is demonstrated for the first time in 40 nm LP CMOS technology. This type II integer-N PLL of order four includes an injection-locked divide-by-4 prescaler and two quadrature series-coupled VCOs, operating in 63-70 GHz and 72-81 GHz frequency bands. It achieves -85 dBc/Hz in-band phase noise at 64 GHz, corresponding to -19.4 dBc integrated phase noise, while consuming 60 mA from a 1.1 V supply.