Strained Silicon Directly on Insulator N- and P-FET nanowire transistors

Abstract

High-performance strained Silicon-On-Insulator (sSOI) nanowire (NW) transistors with gate length and NW width down to 15 nm are reported. We demonstrate sSOI π-Gate n-FET NWs with I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> current of 1410 μA/μm (when I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> = 70 nA/μm) at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> =0.9V and a good electrostatic immunity (DIBL = 140 mV/V, SS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SAT</sub> = 76 mV/dec). Effectiveness of sSOI substrates for n-FETs is shown with an I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> improvement up to +40% at short gate lengths. More generally, size- and orientation-dependent strain impact on electron and hole transport in long and short channel π-Gate (s)SOI NW transistors is systematically studied.