2007 · 270 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringLow-power DesignMemorySemiconductor DevicesLeakage Power ReductionLow-power Digital Circuit DesignMemory DevicesMemory Subsystem DesignPower ManagementData ComparisonLow-power Memory ArchitectureLow-power Memory CircuitsMemory Circuit DesignPhase-change MemoryPower ConsumptionPower-efficient Memory DesignRandom-access Memory
Phase‑change RAM typically consumes high write power due to large currents needed for long write times. The paper proposes a low‑power phase‑change RAM that employs a data‑comparison write scheme. The DCW scheme first reads the stored data during a write operation and writes the new data only if it differs, implemented on a 1K‑bit 128×8‑bit test chip fabricated in 0.8 µm CMOS with 0.5 µm GST cells. This approach halves the write power consumption.
A low power PRAM using a data-comparison write (DCW) scheme is proposed. The PRAM consumes large write power because large write currents are required during long time. At first, the DCW scheme reads a stored data during write operation. And then, it writes an input data only when the input and stored data are different. Therefore, it can reduce the write power consumption to a half. The 1K-bit PRAM test chip with 128×8bits is implemented with a 0.8μm CMOS technology with a 0.5μm GST cell.
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Enhanced write performance of a 64Mb phase-change random access memory
Hyung-Rok Oh, Beak-Hyung Cho, Woo Yeong Cho et al. · 2005 · 11 citations
Engineering, Computer Engineering, Electrical Engineering +13