A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme

TLDR

Phase‑change RAM typically consumes high write power due to large currents needed for long write times. The paper proposes a low‑power phase‑change RAM that employs a data‑comparison write scheme. The DCW scheme first reads the stored data during a write operation and writes the new data only if it differs, implemented on a 1K‑bit 128×8‑bit test chip fabricated in 0.8 µm CMOS with 0.5 µm GST cells. This approach halves the write power consumption.

Abstract

A low power PRAM using a data-comparison write (DCW) scheme is proposed. The PRAM consumes large write power because large write currents are required during long time. At first, the DCW scheme reads a stored data during write operation. And then, it writes an input data only when the input and stored data are different. Therefore, it can reduce the write power consumption to a half. The 1K-bit PRAM test chip with 128×8bits is implemented with a 0.8μm CMOS technology with a 0.5μm GST cell.