Data flow processor chip for image processing

Abstract

An Image Pipelined Processor (ImPP) with high-speed processing capability has been developed utilizing a data-flow architecture strongly emphasizing pipeline processing technique. Moreover, a ring-shaped ImPP array forms a multiprocessor system by itself for higher processing performance. Pipeline processing is especially suitable for operations on streams (sequences of data). Most image processing includes these operations. The ImPP is composed of ten pipeline modules. These are connected with each other in pipeline manner, that is, a one-directional bus is mainly used between two modules for transmitting a token composed of data value and several control signals. All modules can be individually designed in parallel only with the token information. This hierarchical design approach contributes to easier chip development by using CAD systems. The ImPP is a 6.96 mm × 6.99 mm single die, containing over 115 000 transistors with advanced 1.75-µm NMOS technology, as one data-flow processor chip. It operates at 10-MHz clock rate and takes 200 ns for each pipeline stage. To make the application program development convenient, an ImPP assembler has also been developed. Using this assembler, several image processing programs have been prepared and simulated. The ImPP architecture and its processing capability are discussed based on this simulation result.