An FPGA Architecture of Stable-Sorting on a Large Data Volume : Application to Video Signals

Abstract

This paper proposes a single-chip scalable and compact field programmable gate array (FPGA) based architecture of a modified counting sort algorithm which specifically addresses the issue of sorting large volume of integer or fractional data. The proposed architecture is successfully co-simulated with C/MATLAB and VHDL. Performance analysis shows that our approach achieves orders of magnitude performance improvements over the existing hardware-based methods and pure software-based implementations. The area utilization and timing performance of the proposed sorting core are invariant to the number of keys (N), but to the number of bits (k) in N. The design is easily placed and routed to run with a clock rate of 133 MHz while utilizing minimal hardware resources and power. The proposed architecture is verified for performance and accuracy on a Virtex II-Pro FPGA evaluation platform.