2002 · 35 citations · 0 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureField-programmable Gate ArraysReconfigurable ComputingAccelerator ArchitectureDigital Signal ProcessingField-programmable Gate Array ArchitectureFpga ArchitectureHardware AccelerationImage FilteringDigital Filtering ArchitecturesDigital Signal Processing Block ArchitectureDigital Signal Processing BlocksEmbedded Signal ProcessingHardware-based FilteringMedian FilteringReal-time Hardware ArchitectureSignal Processing Accelerators
This paper gives the algorithm and implementation details of a sliding real time 3/spl times/3 median filter. The design is implemented on a Xilinx XC4010 FPGA chip. It is tested and integrated at ER&DC, Trivandrum. The design is tailored to exploit certain features of sliding windows. The Algorithm used to implement median filter is very efficient and implementation results show the significant improvements in operating frequency and hardware requirements over general purpose techniques.