SOI FinFET compact model for RF circuits simulation

Abstract

A methodology to properly establish an accurate SOI FinFET compact model through SPICE simulator is presented. This compact model is implemented in Verilog-A to simulate the performance of RF circuits based on SOI FinFET technology. It predicts well static behavior of the transistor and circuit, as well as their small-signal RF behavior by modeling the intrinsic capacitances and also the effects of the gate resistance and the extrinsic gate capacitances. Finally, the comparison between the simulated and measured performance of a Low Noise Amplifier demonstrates the validity and the capabilities of this compact model to simulate the dc and RF behavior of RF circuits.