IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2013 · 31 citations · 14 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureLow-power DesignMicroelectronicsChannel CodingParallel ArchitecturesSolid-state Drive ArchitectureComplexityDecoder DesignDecoding ComplexityFlash MemoryFlash Memory DevicesLow-latency DesignMemory Latency OptimizationNand Flash Memory
This paper presents a high-throughput and low-complexity BCH decoder for NAND flash memory applications, which is developed to achieve a high data rate demanded in the recent serial interface standards. To reduce the decoding latency, a data sequence read from a flash memory channel is re-encoded by using the encoder that is idle at that time. In addition, several optimizing methods are proposed to relax the hardware complexity of a massive-parallel BCH decoder and increase the operating frequency. In a 130-nm CMOS process, a (8640, 8192, 32) BCH decoder designed as a prototype provides a decoding throughput of 6.4 Gb/s while occupying an area of 0.85 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="TeX">${\rm mm}^{2}$ </tex-math></inline-formula> .
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On-chip error correcting techniques for new-generation flash memories
Stefano Gregori, A. Cabrini, O. Khouri et al. · Proceedings of the IEEE · 2003 · 126 citations
Engineering, Computer Engineering, Electrical Engineering +17