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Multi-level p+ tri-gate SONOS NAND string arrays
18
Citations
1
References
2006
Year
Unknown Venue
Electrical EngineeringNm Gate LengthEngineeringHigh-speed ElectronicsVlsi DesignNanotechnologyTri-gate Silicon-oxide-nitride-oxide-siliconFlash MemoryApplied PhysicsComputer EngineeringSemiconductor Device FabricationSemiconductor MemoryIntegrated CircuitsP+ GateMicroelectronicsSemiconductor Device3D Memory
Tri-gate silicon-oxide-nitride-oxide-silicon (SONOS) NAND string arrays with p+ gate for multi-level high density data flash applications have been fabricated down to 50 nm gate length for the first time. Thick nitride and top oxide layers have been chosen to achieve large threshold voltage shifts of DeltaV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> = 6 V at NAND flash compatible times and voltages. In spite of the thick dielectric stack device scalability is not compromised, as shown by simulation for 30 nm gate length. In addition, excellent program inhibit and retention properties as well as tight multi-level threshold voltage distributions have been found
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