Double-Gate Strained-Ge Heterostructure Tunneling FET (TFET) With record high drive currents and ≪60mV/dec subthreshold slope

TLDR

Tunnel FETs face challenges in achieving sub‑60 mV/dec subthreshold slopes, high ON currents, and mitigating ambipolar behavior. The study aims to develop a comprehensive TFET simulator to address ambipolar behavior and assess scalability. The authors built a quantum‑transport simulator incorporating non‑local BTBT, full bandstructure, and all transition mechanisms, and used it to analyze three asymmetric double‑gate TFET designs. Experimentally, the double‑gate strained‑Ge heterostructure TFET achieved record 300 µA/µm drive current and ~50 mV/dec subthreshold slope, and simulation studies showed that asymmetric DG configurations can suppress ambipolar behavior while maintaining high ON and low OFF currents.

Abstract

The main challenges for Tunnel FETs are experimentally demonstrating SS<60 mV/dec, high ON currents and solving their ambipolar behavior. We have experimentally demonstrated a Double-Gate, Strained-Ge, Heterostructure Tunneling FET (TFET) exhibiting very high drive currents and SS<60 mV/dec. Due to small bandgap of s-Ge and the electrostatics of the DG structure, record high drive current of 300 uA/um (the highest ever reported experimentally for a TFET) and a subthreshold slope of ~50 mV/dec was observed. In addition, to address the ambipolar problem and examine the scalability of TFETs, we have developed a sophisticated TFET simulator that uses a Quantum transport model, Non-local BTBT, complete Bandstructure (real and complex) information, and includes all transitions (direct and phonon assisted). Using this simulator, we have studied the scalability of three asymmetric DG TFET configurations (underlapped drain, lower drain doping and lateral heterostructure) in terms of their ability to solve the ambipolar behavior and achieve high ON and low OFF currents.