IEEE Transactions on Computers · 1974 · 17 citations · 5 references
EngineeringComputer ScienceElectrical EngineeringCircuit TheoryFault-tolerant ComputingFault-tolerant SystemsCombinational Logic DescriptionDesign For TestabilityFault DetectionFault DiagnosisReliable System DesignCircuit Fault AnalysisCombinational Logic DesignCombinatorial TestingFault MaskingMinimal Sets
The problem of how to determine minimal sets of tests for single and multiple faults in irredundant combinational circuits is dealt with. It is shown that the "Equivalent Sum of Products" form of the given network contains all the information necessary to derive a min; mal test set. A simple procedure which generates a minimal test set Ts for single faults is described. Fault masking is then studied and it is shown how to find the multiple faults undetected by Ts. Finally a method which derives a nearly minimal multiple fault test set Tm where Ts [mi][/mi] Tm is given.
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