Monolayer $\hbox{MoS}_{2}$ Transistors Beyond the Technology Road Map

Abstract

The performance of a 5-nm gate length monolayer MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> transistor is benchmarked against an ultrathin body Si transistor of similar dimensions and the ITRS requirements for 2026 low operating power (LOP) technology. The MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> transistor has a subthreshold slope of 70 mV/dec, an on -/off-current ratio of 4.8 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> , a drive current of 238 μA/μm, a peak transconductance of 2.65 mS/μm, a total capacitance of 0.164 fF/μm, and an intrinsic switching delay of 0.276 ps. These numbers for the silicon competitor are 79 mV/dec, 1.8 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> , 89 μA/μm, 1.22 mS/μm, 0.0733 fF/μm , and 0.331 ps, respectively. The heavier effective mass of the MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> significantly reduces the direct source-drain leakage current, and it increases the drive current and the transconductance. The performance metrics of MoS <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> transistor are comparable to the ITRS 2026 LOP technology requirements.