Optimization of VDD and VTH for low-power and high speed applications

TLDR

Closed‑form formulas are presented to determine the optimum supply voltage (VDD) and threshold voltage (VTH) that minimize power dissipation given technology parameters and required speed. The authors derive closed‑form formulas that account for short‑channel effects, VTH variation, and temperature to compute the optimum VDD and VTH for a given technology and speed. The study demonstrates that setting the leakage‑to‑total power ratio near 30% optimizes power, and that the optimum VDD aligns with the SIA roadmap while the optimum VTH for logic blocks at high temperature and low process variation lies between 0 V and 0.1 V across generations.

Abstract

Closed-form formulas are presented for optimum supply voltage (VDD) and threshold voltage (VTH) that minimize power dissipation when technology parameters and required speed are given. The formulas take into account short-channel effects and the variation of VTH and temperature. Using typical device parameters, it is shown that a simple guideline to optimize the power consumption is to set the ratio of maximum leakage power to total power about 30%. Extending the analysis, the future VLSI design trend is discussed. The optimum VDD coincides with the SIA roadmap and the optimum VTH for logic blocks at the highest temperature and at the lowest process variation corner is in the range of 0V~0.1V over generations.