Two-million-pixel SOI diode uncooled IRFPA with 15μm pixel pitch

TLDR

The authors developed a 2‑million‑pixel, 15 µm‑pitch SOI diode uncooled IRFPA array. Using a shrinkable 2‑in‑1 SOI diode pixel design combined with stitching, the 40.30 mm × 24.75 mm chip achieves a 2‑million‑pixel array with ten‑series diodes per pixel, four‑output readout enabling 30 Hz, and designed NETDs of 60 mK (15 Hz) and 84 mK (30 Hz) with a 12 ms thermal time constant. Fabrication confirmed the array operates at 30 Hz with NETD of 65 mK (15 Hz) and a 12 ms thermal time constant, matching the design and maintaining performance despite the pixel count increase.

Abstract

We report the development of a 2-million-pixel, that is, a 2000 x 1000 array format, SOI diode uncooled IRFPA with 15 μm pixel pitch. The combination of the shrinkable 2-in-1 SOI diode pixel technology, which we proposed last year [1], and the uncooled IRFPA stitching technology has successfully achieved a 2-million-pixel array format. The chip size is 40.30 mm x 24.75 mm. Ten-series diodes are arranged in a 15 μm pixel. In spite of the increase to 2-million-pixels, a frame rate of 30 Hz, which is the same frame rate as our former generation (25 μm pixel pitch) VGA IRFPA, can be supported by the adoption of readout circuits with four outputs. NETDs are designed to be 60 mK (f/1.0, 15 Hz) and 84 mK (f/1.0, 30 Hz), respectively and a τ_th is designed to be 12 msec. We performed the fabrication of the 2-million-pixel SOI diode uncooled IRFPAs with 15 μm pixel pitch, and confirmed favorable diode pixel characteristics and IRFPA operation where the evaluated NETD and τ_th were 65 mK (f/1.0, 15 Hz) and 12 msec, respectively.