Concepedia

Abstract

A proprietary scheme for a unified memory system that covers all design aspects to ensure fast display and quick computation is presented. This device replaces extant memory types and their interconnects with unique DRAMs, a high-performance, chip-to-chip interface, and a high speed channel. It delivers a byte of data every 2 ns for a block of information up to 256 bytes long. The features and performance of this DRAM are described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>